1. Field of Invention
The present invention relates to a capacitor in a semiconductor device and a fabricating method thereof, more particularly, to an upper electrode of a capacitor and a fabricating method thereof which reduce leakage current and secure the stable thickness of the upper electrode of a three-dimensional capacitor by inserting an extra TiN layer free from Cl at an interface between an upper electrode and a dielectric layer in a capacitor, of which dielectric layer is made of Ta.sub.2 O.sub.5 and of which upper electrode is made of TiN, for a semiconductor memory device.
2. Discussion of Related Art
Cell areas are reduced as a semiconductor device needs ultra-high integrity. Thus, many studies for increasing the capacitance of a capacitor are being developed. There are various ways of increasing the capacitance such as forming a stacked or trench typed three dimensional structure, whereby a surface area of a dielectric layer is increased.
In order to constitute a cell area in a DRAM fabrication, transistors and the like are formed on a semiconductor substrate, storage and plate electrodes of polycrystalline silicon and a dielectric layer are formed wherein the dielectric layer lies between the electrodes, and metal wires are formed to connect the devices one another. When an upper electrode and a dielectric layer of a capacitor of a metal-insulator-metal or metal-insulator-metal are formed with TiN containing Cl and Ta.sub.2 O.sub.5, respectively, the optimization of annealing the dielectric layer of Ta.sub.2 O.sub.5 for improving the characteristic of the dielectric layer and another optimization of forming the upper electrode without Cl are proposed to control the leakage current of a capacitor.
TiN is mainly used for an upper electrode of a capacitor provided that a dielectric layer is formed with Ta.sub.2 O.sub.5. MO(metal-organic)CVD-TiN is formed by using metal-organic source such as TDMAT or TDEAT by CVD(chemical vapor deposition). And, TiCl.sub.4 --TiN having a polycrystalline structure is formed by reacting TiCl.sub.4 of an inorganic source with NH.sub.3.
TiCl.sub.4 --TiN, as a substance for an upper electrode, is superior to MOCVD-TiN because step coverage of TiCl.sub.4 --TiN is better than that of MOCVD-TiN. Besides, when a TiN layer is formed by TDMAT of the metal-organic source, carbons contained in the TiN layer migrates into a dielectric layer of Ta.sub.2 O.sub.5. Thereby, the characteristic of the dielectric layer is ruined. When a dielectric layer is formed with Ta.sub.2 O.sub.5 and an upper electrode is formed with a TiCl.sub.4 --TiN layer by CVD, Cl remains at an interface between the Ta.sub.2 O.sub.5 layer and the TiN layer as well as inside the TiN layer. Cl breaks down a portion of the Ta.sub.2 O.sub.5 layer to form a path of leakage current with Ta which is a good conductive substance of metal. Thereby, the characteristic of the dielectric layer of Ta.sub.2 O.sub.5 is ruined when a capacitor is operated.
FIG. 1 to FIG. 3 show cross-sectional views of fabricating a capacitor in a semiconductor device according to a related art.
Referring to FIG. 1, an impurity region 11 used as a source or drain region is formed by doping a predetermined portion of a silicon substrate 10 of p typed semiconductor heavily with n typed impurities such as As, P or the like.
A silicon oxide layer 12 as an insulating interlayer 12 is formed on the silicon substrate by chemical vapor deposition(hereinafter abbreviated CVD).
A contact hole exposing a surface of the impurity region 11 is formed by removing a portion of the insulating interlayer 12 by photolithography.
A conductive layer of W is formed on the insulating interlayer 12 to fill up the contact hole by CVD. A contact plug 13, which is connected electrically to the impurity region 11 and fills up the contact hole, is formed by etching back the conductive layer of W until a surface of the insulating interlayer is exposed.
A polycrystalline silicon layer doped with impurities is deposited on the insulating interlayer 12 including an exposed surface of the plug 13 by CVD. Then, a storage electrode 14 is formed by patterning the polycrystalline silicon layer by photolithography of dry etch. In this case, the storage electrode 4 may be patterned as one of various shapes such as a box, crown, cylinder, fin and the like.
Referring to FIG. 2, a dielectric layer 15 is formed by depositing Ta.sub.2 O.sub.5, of which dielectric constant is excellent, on an exposed surface of the storage electrode 14. Then, the characteristics of the dielectric layer 15 are improved by annealing the dielectric layer under oxygen ambience. This is because the dielectric layer 15 mainly consisting of Ta.sub.2 O.sub.5-x needs to be saturated into Ta.sub.2 O.sub.5 to provide an ideal dielectric constant.
Referring to FIG. 3, an upper electrode which is a plate electrode is formed by depositing a TiN layer 16 on the dielectric layer 15 including the insulating interlayer 12. In this case, the TiN layer 16 is made of TiCl.sub.4 --TiN which is formed by reacting TiCl.sub.4 of an inorganic source with NH.sub.3 on the dielectric layer 15.
Accordingly, when the upper electrode is formed with a TiCl.sub.4 --TiN layer by CVD, Cl remains at an interface between the Ta.sub.2 O.sub.5 layer and the TiN layer as well as inside the TiN layer, thereby ruining the characteristic of the dielectric layer of Ta.sub.2 O.sub.5.
Moreover, stress-induced leakage current is brought about by tensile stress amounting to 1E10 to 9E10 dyne/cm.sup.2 due to the grain structure of the TiCl.sub.4 --TiN layer.